1. Field of the Invention
The present invention relates to an address generation system for use in data processors, and more specifically, to an address generation system for accessing an operand used in instruction execution.
2. Description of Related Art
Heretofore, as concerns the addressing of memory in which operands are stored the following two methods have been wellknown. The first method is a so-called "pre-decrement system" in which before address generation for accessing operand a content of a register is substracted by the value indicated by the word length and so on, and the substracted value is used as an address of operand. The second method is a so-called "post-increment system" in which the content of a register is used as it is for address generation, and thereafter the content of the register is added with the value indicated by the word length and so on, and the added value is written back into the same register. The pre-decrement system and post-increment system will be generically called "register modify type" or "register modification type" hereinafter.
Referring to FIG. 1, there is shown one example of a conventional address generation control apparatus of the register modify type. The shown control apparatus includes a decoder 31 receiving an addressing field 311 contained in a given instruction code for indicating various items of address generation. A decoded signal is applied to a register control circuit 32 through a decoded signal line 312. This control circuit 32 responds to the information on the decoded signal line 312 to control the read/write of an associated group of registers 33 through a control line 314 and the operation of an associated incrementer/decrementer 34 through another control line 313. The group of registers 33 includes at least one register adapted to hold an address for accessing operand used in an instruction execution, and is coupled to the incrementer/decrementer 34 through a data line 315. The incrementer/decrementer 34 operates, under the control of the control circuit 32, to increment or decrement the content of the data outputted on the data line 315 from one register of the register group 33. When an instruction is executed in an execution unit 35, the register group 33 and the incrementer/decrementer 34 are controlled by an execution control unit 36.
In the address generation control apparatus as mentioned above, when the decoder 31 decodes the address field 311 in a given instruction code, if a register modification is detected, the control circuit 32 responds to the data on the decoded signal line 312 so as to carry out the following control operation.
In the case of pre-decrement, the control circuit 32 controls the register group 33 through the control line 314 so that the content of a register designated by the decoded data is outputted to the data line 315. Then, the control circuit 32 operates the incrementer/decrementer 34 through the control line 313, so that the incrementer/decrementer 34 reads and decrements the data on the data line 315 and outputs the decremented data to the data line 315. The decremented data on the data line 315 is written under the control of the control circuit 32 back to the register from which the data has been read out to the data line 315. Thereafter, the decremented data in the same register is read and outputted through a data line 316 to an address adder (not shown).
In the case of post-increment, the content of a register by the decoder 31 is read to the data line 316 and then supplied to the address adder. On the other hand, the content of the same register is also outputted through the data line 315 to the incrementer/decrementer 34. The incrementer/decrementer 34 operates under the control of the control circuit 32 to increment the data supplied through the data line 315 and to output the incremented data back to the data line 315. As a result, the incremented data is written back to the register from which the data has been read out to the data lines 315 and 316.
In the above mentioned address generation control circuit, when a register modification control is carried out for address generation of operands, it is necessary to modify the content of a register provided in the execution unit 35 every time the register modification is designated for address generation of operand. If one instruction contains two or more operands, every time the register modification is designated in the course of the address generation of the operands, the increment/decrement operation has to be performed to modify the content of the register concerned. Accordingly, in the case that instructions are processed in a pipeline manner with two units, i.e., an instruction decode/address computation unit and the instruction execution unit, even if the instruction decode/address computation unit is required to modify a register in the instruction execution unit, if the instruction under execution in the execution unit involves the register which is required to be modified, the address computation cannot be carried out until the use of the register concerned has been completed in the instruction execution unit. Otherwise, the content of the register concerned would be changed before it is used in the instruction execution unit. Namely, the pipeline operation is temporarily stopped.
In the past, in order to solve the above mentioned problem, there has been proposed to provide in the instruction decode/address computation the same register group as that provided in the instruction execution unit, so that the register modification can be controlled independently of the instruction execution unit. However, to realize this method, the scale of the register becomes too large. In addition, when one register is written in the instruction execution unit, the content of that register must be copied to the corresponding register provided in the instruction decode/address computation unit. To the contrary, if the content of one register is modified in the instruction decode/address computation unit, the modified content of that register must be copied to the corresponding register provided in the instruction execution unit. Therefore, the control of the registers becomes too complicated.